The present invention generally relates to an image data processing apparatus, and more particularly to an image data processing apparatus in which binary input image data is converted into encoded output data. The encoded output data is used in facsimile systems, database systems and the like.
A picture coding method for converting a stream of binary image data into encoded data based on the probabilities of occurrence of the values 1 and 0 is known. There is an image data processing apparatus in which this picture coding method is utilized. In the above mentioned apparatus, in synchronism with a clock signal of a prescribed period, a set of coincidence signals derived from the input image data is input to a set of registers. The level of each coincidence signal indicates whether or not one of neighborhood pixels surrounding the target pixel in the input image data is coincident with one of predetermined reference dots at given locations relative to the location of the target pixel. When the coincidence mentioned above occurs, a low-level coincidence signal is provided. When the coincidence does not occur, a high-level coincidence signal is provided.
In the above mentioned apparatus, each register performs a counting of the pixel coincidences in accordance with coincidence signals received at the register. The number of the registers is the same as the number of the reference dots, and each register contains a count value indicating the number of coincidences with respect to the corresponding dot among the reference dots. In the picture coding process as mentioned above, it is necessary to detect which pixel of the neighborhood pixels of the current target pixel having a certain relationship with the next target pixel to be encoded. The next target pixel appears in the stream of the input image data after the current target pixel. In order to detect which pixel has the certain relationship mentioned above, it is necessary to locate a register having the highest coincidence count among the registers in the above mentioned apparatus.
FIG. 1 shows a conventional image data processing apparatus for detecting the location of a reference dot having a certain relation with a next target pixel to be encoded. In the image data processing apparatus shown in FIG. 1, four coincidence signals CN0-CN3 derived from input image data are respectively input to four registers 1-4 in synchronism with a clock signal having a prescribed period. In this apparatus, the comparisons for the count values in the registers 1-4 are repeatedly performed by means of three comparators 5-7, and the register having the highest count value is selected from among the four registers 1-4 by means of three selectors 8-10. The selector 10 outputs a signal MAX indicating the count value of the corresponding highest-value register.
More specifically, in the image data processing apparatus shown in FIG. 1, the four coincidence signals CN0-CN3 are respectively input to the four registers 1-4. A count-value signal, which indicates the number of coincidences (the count value) at the corresponding reference pixel counted by the corresponding register, is output from each of the two registers 1 and 2 to the comparator 5. A select signal 1 indicating which of the two registers contains the higher count value is output by the comparator 5. The output select signal of the comparator 5 is input to the selector 8, so that the register containing the higher count value is selected by the selector 8. The selector 8 outputs a signal indicating the count value of the selected register to the comparator 6.
The output signal of the selector 8 and the output signal of the register 3 are input to the comparator 6, so that the count value selected by the selector 8 is compared with the count value of the register 3. A select signal 2 indicating which register contains the higher count value is output by the comparator 6. The output signal of the comparator 6 is input to the selector 9. Similarly, the selector 9 outputs a signal indicating the count value of the selected register to the comparator 7. The same procedure is repeated by the comparator 7 and the selector 10. Finally, in the image data processing apparatus shown in FIG. 1, the selector 10 outputs the signal MAX indicating the highest count value among the count values of the registers 1-4.
The select signals 1-3 received from the comparators 5-7 may be decoded in order to detect which of the four registers contains the highest count value. By receiving the signal MAX from the selector 10, it is possible to find the the highest count value among the count values counted by the four registers.
However, the image data processing apparatus as shown in FIG.1 requires a number of comparators and a number of selectors. The number of the required comparators (or selectors) is smaller than the number of registers by only one. There is the demand for high-performance image data processors in the industry. When the number of bits of the data signal processed by each comparator (or each selector) is increased, or when the number of the input coincidence signals is increased and therefore the number of the registers is increased, the above mentioned image data processing apparatus becomes larger in size, and the manufacturing cost becomes higher.